In recent years, with reduction in size and thickness of portable devices and others having semiconductor devices mounted thereon, demands for reducing the size and thickness of the semiconductor devices have been increasing.
Japanese Patent Application Laid-Open No. 2000-315776 discloses a semiconductor device configured to have a plurality of semiconductor chips mounted into one package to support large capacity.
Japanese Patent Application Laid-Open No. 2012-230981 discloses a semiconductor device having at least two semiconductor chips mounted thereon and effective in reducing the amount of warpage occurring between the semiconductor chips and stabilizing a warpage shape.
When a plurality of semiconductor chips are mounted so as to be arranged in parallel on a wiring substrate and have resin casted therein, it is required to determine a space between semiconductor chips in consideration of filling ability of sealing resin so as to also fill between the semiconductor chips with resin. Thus, in a general semiconductor device manufacturing method, a certain space, for example, a space on the order of 0.2 mm, is required on the wiring substrate, and reduction in size of the wiring substrate has a limitation. Moreover, in the general semiconductor device manufacturing method, a plurality of semiconductor chips is mounted one by one over the wiring substrate, and therefore the number of processes increases accordingly, thereby posing a problem of inefficiency at the time of manufacture.
However, these problems are not considered in the above-described Japanese Patent Application Laid-Open No. 2000-315776 and Japanese Patent Application Laid-Open No. 2012-230981. For example, while Japanese Patent Application Laid-Open No. 2012-230981 points out that a two-bump-shaped recessed warpage occurs when two semiconductor chips are arranged with a space of 2.5 mm, a reduction in size of a wiring substrate, an improvement in manufacturing efficiency, and so forth are not considered.
Therefore, the emergence of a semiconductor device supporting reduction in size and thickness and having high manufacturing efficiency is desired.